A phase change memory or phase change random access memory (PRAM) as referred to herein is also referred to as an ovonic unified memory (OUM) in the art. The OUM is based on a chalcogenide alloy, which, after being heated and cooled, adopts one of two stable but programmable phases: polycrystalline or amorphous. Resistance of the first phase, i.e., the polycrystalline phase, is low, and resistance of the second phase, i.e., the amorphous phase, is high. A logical one (1) or zero (0) depends on the phase of the programmable volume, determined by measuring its resistance. The crystalline or conductive state is the set or 0 state; and the amorphous or resistive non-conductive state is the reset or 1 state.
To make the programmable volume amorphous, it is heated above its melting point by a resistive heater. It cools rapidly when the heater is turned off. To make it crystalline, it is heated to just below its melting point for a short period of time, e.g., 50 ns, so that the atoms line up in their crystalline locations.
The key to the phase change memory is the chalcogenide material. The device includes an alloy of germanium (Ge), antimony (Sb) and tellurium (Te), which is referred to commonly as a GST alloy. The material is useful as a memory device because of its ability to switch rapidly, when heated and cooled, between the stable amorphous (reset or 1 state) and crystalline phases. In the amorphous phase, the material has low reflectivity and high resistance. In the crystalline phase, it is reflective and has a low resistance.
A memory cell that incorporates the chalcogenide material typically includes a top electrode, a layer of the chalcogenide, and a resistive heating element. Reading the programmed cell is done by measuring its resistance. To write data to a cell, the chalcogenide is heated past its melting point and then rapidly cooled to make it amorphous. To make it crystalline, it is heated to just below its melting point and held there for a short period of time, giving the atoms in the material time to position themselves in their crystal locations.
FIG. 1 is a schematic diagram illustrating a memory cell 10 which uses the programmable chalcogenide material. The cell 10 includes a conductive top electrode 12 formed over the programmable phase change chalcogenide material 14. A conductive bottom electrode contact (BEC) 16 connects the top electrode 12 and programmable material 14 to a conductive bottom electrode 18.
FIGS. 2A and 2B are schematic diagrams which illustrate the cell 10 in each of the two programmed states. In FIG. 2A, the cell 10 is shown in the conductive set or 0 state. In this state, the programmable material 14 is in the crystalline state. In FIG. 2 B, the cell 10 is shown in the resistive reset or 1 state. In this state, the programmable material 14 is in the amorphous state. Each of FIGS. 2A and 2B also shows the access transistor 20 used in controlling the flow of current through the cell 10. As current flows through the cell 10, the BEC behaves as a resistive heater which heats the volume of programmable material to alter its state.
FIG. 3 is a schematic diagram illustrating the electrical configuration of the cell 10. In FIG. 3, the cell is referred to as “C.” A word line WL controls activation of the cell C. The current through the cell, ICEL, and bit line BL serves to program the device 10.
FIG. 4 is a timing diagram illustrating programming of a memory cell that includes a programmable chalcogenide material. The timing diagram of FIG. 4 is a graph of temperature over time illustrating the programming pulses for programming the material to the set (crystalline) state and the reset (amorphous) state, in accordance with programming approaches of the prior art. The curve labeled 35 illustrates the temperature-time relationship for the reset pulse, i.e., the temperature pulse used to program the material to the reset (amorphous) state; and the curve labeled 36 illustrates the time-temperature relationship for the set pulse, i.e., the temperature pulse used to program the material to the set (crystalline) state.
Referring to the curve labeled 35 in FIG. 4, to change the programmable volume of chalcogenide material to the amorphous phase (reset state), the chalcogenide alloy is heated to a temperature above its melting point (Tm) by a resistive heater. The heating pulse is applied for a relatively short period of time, e.g., a few nanoseconds. The alloy cools rapidly when the heater is turned off. Referring to the curve labeled 36, to change the programmable volume to the crystalline phase (set state), the alloy is heated to a temperature below its melting point. As shown in the figure, the temperature to which the alloy is heated is within a set window between a crystallization or curing temperature Tx and the melting temperature Tm. The elevated temperature is maintained in the set window for a time period of about 50 ns to allow the alloy to crystallize, that is, to allow the atoms in the material to align in their crystalline structure. After the crystallization takes place, the set pulse is removed, and the material cools.
FIG. 5 is a graph illustrating the current-voltage (I-V) characteristics of the PRAM cell using the chalcogenide material for a cell in the set state and the reset state. The curve labeled 37 shows the I-V characteristic for a cell in the set state, and the curve labeled 38 shows the I-V characteristic for a cell in the reset state. The PRAM is programmed by a current pulse at a voltage above a switching threshold voltage Vt. The programming pulse drives the memory cell into a high or low resistance state, which depends upon the magnitude of the current. Information stored in the cell is read out by measuring the cell's resistance. Read operations are performed at a voltage below the threshold voltage Vt to avoid error potentially caused by inadvertent phase alteration of the material.
FIG. 6 is a timing diagram of a set pulse used conventionally to program phase-change memory elements to the set state. The set pulse is applied to a bit line to program phase-change memory elements to the set state. The set pulse duration T2-T1 in the conventional technology is constant.
FIG. 7 is a graph of cell resistance versus time during programming of a phase-change memory cell from a reset state to a set state for a normal condition (condition A) and an error condition (condition B). The resistance of the cell in the reset state is referred to as RRESET, and the resistance of the cell in the set state is referred to as RSET. The value of RRESET is generally determined by the size of the bottom electrode contact (BEC) 18 of the device. The curve labeled 41 is for a memory cell A in a normal reset state being programmed to the set state. The curve labeled 42 is for a second memory cell B in an abnormal reset state being programmed to the set state. The cell B is in an abnormal reset state in that its reset resistance RRESETB is abnormally high.
Referring to curve 41, in the reset state, the resistance in cell A is a normal level RRESETA. At time T1, the set pulse is activated. As the cell is heated, its resistance drops as shown. The resistance crosses the resistance threshold reference as it transitions to the set state. The reference defines the cell resistance boundary between the reset state and the set state. At time T2, after the cell A reaches the set state, the set pulse is removed. The cell cools and remains in the set state, at a normal set resistance of RSETA.
Referring to curve 42, the resistance of the cell B begins at the abnormally high level of RRESETB. At time T1, the set pulse is applied, and the resistance of the cell begins dropping. Because the duration of the set pulse window is predefined and set at a constant, at time T2, the set pulse is removed. However, in this case, because the resistance in the reset condition was abnormally high, the duration of the set pulse was not long enough to allow the resistance of the cell to decrease past the reference level such that the cell could enter the set state. Instead, the set pulse is removed at T2 while the cell resistance RSETB is still above the reference. When the cell cools, the resistance RSETB remains above the reference. As a result, the cell has not been correctly programmed to the set state. That is, a cell programming error has occurred.
Thus, because the set pulse duration is constant, errors in the PRAM programming may occur because the value of RSET may vary depending on the value of RRESET. Specifically, if the value of RRESET is high, then the value of RSET may be too high after set programming to be stable in the set state.